The invention relates to technology for designing and verifying an electronic design, such as the design of an integrated circuit (“IC”).
Modern electronic design is typically performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language (HDL). Common examples of HDLs include Verilog and VHDL. An EDA system typically receives the high level behavioral descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction. Essentially, the process to implement an electronic device begins with functional design and verification (e.g., using RTL), and then proceeds to physical design and verification.
Circuit designers and verification engineers use different methods to verify circuit designs. One common method of verification is the use of simulation. Simulation dynamically verifies a design by monitoring behaviors of the design with respect to test stimuli. For many types of designs, simulation can and should be performed during the design process to ensure that the ultimate goals are achievable and will be realized by the finished product. The exploding demand for high performance electronic products has increased interest in efficient and accurate simulation techniques for integrated circuits. For analog designs, an analog-based simulation approach such as SPICE is commonly used to implement simulation of the design. For digital circuit, equivalent digital simulation is performed.
There are many types of electrical analyses that need to be performed to ensure the proper operation of an electronic design. For example, it is often desirable to analyze power distribution networks to check for potential problems relating to IR drops and electromigration effects. Power distribution networks are used to distribute power and ground voltages from pad/package locations to circuit blocks in a design. Shrinking device dimensions, faster switching frequencies and increasing power consumption in deep submicron technologies can cause large switching currents to flow in the power and ground networks, which degrade performance and reliability.
Due to the resistance of interconnects in the power networks, there is a voltage drop across the network, commonly referred to as IR drop. IR drop is a reduction in voltage that occurs on power supply networks (i.e., VDD) in integrated circuits. IC designs usually assume the availability of an ideal power supply that can instantly deliver any amount of current to maintain the specified voltage throughout the chip. In reality, however, a combination of increasing current per-unit area on the die and narrower metal line widths (which causes an increase in the power-grid resistance) causes localized voltage drops within the power grid, leading to decreased power supply voltage at cells and transistors. These localized drops in the power supply voltage decrease the local operating voltage of the chip, potentially causing timing problems and functional failures. IR drop can be both a local and global phenomena. IR drop can be local phenomenon when a number of cells in close proximity switch simultaneously, causing IR drop in that localized area. A higher power grid resistance to a specific portion of the chip can also cause localized IR drop. IR drop can be a global phenomenon when activity in one region of a chip causes effects in other regions. For example, one logic block may suffer from IR drop because of the current drawn by another nearby logic block.
Electromigration (EM) is an effect on a circuit caused by movement of ions in a conductor structure, which over time will reduce the effective ability and reliability of the conductor to conduct current from one part of the circuit to another. Electromigration could significantly decrease the reliability of an IC, resulting in possible errors and failures in the IC product. With modern reductions in feature sizes made possible by improving manufacturing processes, the probability of failure due to electromigration becomes much more possible due to increases of both the power density and the current density of wiring and power structures.
Therefore, it is important for an EDA verification tool to properly and adequately be able to perform electrical analysis to check for potential IR drop and EM problems.
One approach that can be taken to perform IR drop and EM analysis is a two-stage analysis that involves: (a) first performing simulation to obtain a current through each device path on a power network of interest; and (b) using the current obtained in the first stage to analyze for IR drop and EM problems. However, this approach is problematic for multiple reasons. One problem with this approach is that it assumes a constant VDD voltage is being applied to each device path, which may be a faulty assumption under certain situations and hence may lead to inaccurate results. This may occur, for example, if RC effects cause the applied voltage at a circuit path to differ from VDD, which may result in possibly erroneous analysis results if not taken into account. Another problem with this approach is that the action of solving for probed current values in the first stage requires the currents to be part of solution variables for different partitions of a global circuit analysis by a (Fast-Spice) simulator, which are involved in iterations of the global analysis. This causes extra evaluations of device models which are expensive in terms of CPU time given the large size of modern circuit designs. Thirdly, computed active device currents usually switch very fast, therefore storing the full waveforms of large number of device currents as is required in this approach will require large amount of storage space. Finally, solving in the second stage with high accuracy of a linear RC circuit stimulated by fast switching currents dictates the adoption of very small timesteps. Overly small timesteps will slow down the computation process.
Therefore, there is a need for an improved approach to perform electrical analysis, e.g., to analyze power distribution networks for IR drop and EM problems.